Many integrated circuits such as dynamic random access memory (DRAM) and static random access memory (SRAM) employ fuses. Such can provide for redundancy for the purpose of preventing reduction of yield of the semiconductor devices which may be caused by random defects generated in the manufacturing process. The redundant circuit portion is provided as a spare circuit portion having the same function as a specific circuit portion so that the specific circuit portion which has a defect caused during manufacturing may be replaced with the redundant circuit in order to maintain the function of the entire semiconductor. Moreover, fuse links provide for voltage options, packaging pin out options, or any other option desired by the manufacturer to be employed prior to the final processing. This helps increase yield and makes it easier to use one basic design for several different end products.
One problem associated with fuse structures is that the thickness of the insulating layer over the fuse tends to have very large variation. The large variation in the final insulation thickness is due to variations in the deposition of isolation between a first and a second conductive level, variations in deposition of the next-to-last insulation layers, non-uniformities during chemical-mechanical polishing and variations in the reactive ion etching to achieve the final thickness. Accordingly, the thickness variation occurs because of the cumulative variations of each of the process steps even when each individual step can be reasonably controlled. The variation in thickness in turn limits the fuse pitch to that which corresponds to the largest isolation layer generated by the processing. However, it would be desirable to be able to reduce the pitch as well as controlling its thickness as much as possible. Such a control would permit reducing the fuse pitch and providing more redundancy to memory products.